1. Field of the Invention
The present invention relates to an integrated circuit, and particularly relates to a technique for simultaneously testing a plurality of memories with a BIST (Built-in Self Test) circuit.
2. Description of Related Art
There is an integrated circuit in which multiple memory circuits whose memory cell arrays are different in size and a BIST circuit for running self tests on the multiple memory circuits are mounted on a substrate. In such an integrated circuit, required is a technique for simultaneously testing multiple memory circuits while maintaining a high test quality.
An integrated circuit related to the conventional technique includes multiple memory circuits and an internal address bus connected thereto. Specifically, assume here that a memory circuit in which the total sum of the number of upper address bits and the number of lower address bits is the largest of the memory circuits is set as a reference circuit. Then, the multiple memory circuits are formed such that each of the other memory circuits has upper address bits and lower address bits not more than the reference memory circuit does. In addition, the internal bus is connected to those other memory circuits in a manner that a predetermined number of bits from the most significant bit of the reference memory circuit are sequentially inputted as the upper address, and that a predetermined number of bits from the least significant bit of the reference memory circuit are sequentially inputted as the lower address (refer to Patent Document 1: Japanese Patent Application Laid Open Publication No. 2002-32999). Accordingly, multiple memory circuits can be tested simultaneously without including a dedicated test (BIST) circuit in each memory circuit.
In addition, an integrated circuit according to another conventional technique includes a common test bus connected to multiple memories and multiple bridge circuits each of which converts test data information inputted from the common test bus into one having an access data width unique to the corresponding memory and which supplies the resultant information to the memory. Thereby, the integrated circuit supplies the test data information from the common test bus to the multiple memories in parallel (refer to Patent Document 2: Japanese Patent Application Laid Open Publication No. 2003-346500). This is considered to enable parallel test execution on multiple memories.